Mixed-signal integrated circuits are becoming increasingly prevalent with the continually increasing scale of circuit integration that has spurred the development of system on chip (SOC) design and other types of design integration. Concurrent with increasing integration scale, the operating speeds of circuits has also increased. The increases in both integration scale and speed has raised the complexity and difficulty of testing these circuits and their component circuitry. As a result, design for testability (DFT), built-in self test (BIST) and embedded test core testing schemes have been employed to facilitate testing of these circuits. However, each of these schemes has one or more drawbacks, especially as integration scale and operating speeds continue to increase.
Generally, DFT is a design approach in which integrated circuit designs are partially dictated by testing considerations. Typically, DFT includes providing ready access by automated testing equipment (ATE) to certain portions of the integrated circuits, e.g., by providing externally accessible test pads that allow ATE to communicate with the portion of the circuit being tested. One drawback of DFT is that with increasing speeds, the relatively slow speeds of conventional ATE and the relatively long signal propagation delay attendant the physical distance between the ATE and the circuit under test (CUT) hamper testing. Another drawback is that the manner in which conventional ATE conduct testing reduces testing speeds. For example, conventional ATE may perform a particular test by storing a large amount of measurement data from a particular test and then processing the data after the measurement data has been collected. This sort of testing/processing can result in relatively long testing times, which are undesirable, particularly with high-production circuits.
BIST and embedded testing core schemes are similar to one another in that they require dedicated testing circuits to be added to the integrated circuits. Drawbacks of BIST and embedded testing core schemes include the need to add often-complex testing circuits to the integrated circuits. As levels of integration of SOCs and similar devices increase, the number of additional testing circuits needed likewise increase. Generally, if given a choice, circuit designers would prefer not to utilize valuable chip space for testing circuits.
In view of the foregoing, what are needed, among other things, are a system and method for testing digital/analog integrated circuits, and/or portions of the circuitry thereof, that minimize impact on chip space and minimize testing time, yet are capable of testing high-speed circuits. It is also desirable that, in some embodiments, such a system and method be “backward-compatible” for use with conventional and legacy ATE. The system and method of the present invention satisfy these and other needs.